The present invention generally relates to semiconductor memory devices and data processor devices.
As a conventional example concerning the present invention, there is a flash memory described in a document of IEICE Transactions, vol. E74, pp. 130-141, 1991, written by T. Masuhara et al. This flash memory cell has the source, drain and channel region formed on a silicon substrate surface, and the floating gate and control gate of polycrystalline silicon provided within an insulator. The memory function is achieved by charge accumulation within the floating gate and by use of the change of conductance between the source and drain due to the increase or decrease of the amount of accumulated charges. As another conventional example, a single-electron memory using polycrystalline silicon can be cited which is described in IEEE International Electron Circuit Conference, pp. 541-544, 1993, written by K. Yano et al, and International Solid-State Circuits Conference, pp. 266-267, 1996, written by K. Yano et al. This technology is that the channel as a current path and the electron capturing memory region are simultaneously formed by thin film of polysilicon. Storing of information can be performed by using the fact that the conductance of the current path is changed when an electron is captured by the memory region. In addition, the number of accumulated electrons can be controlled with high precision up to a single unit by accumulating electrons in minute memory regions, and the accumulated electrons can be stably held even at room temperature. This single-electron memory can be found, from its principle, to be suited for its extreme size reduction. Particularly by using an elemental structure having the source and drain regions provided on an insulator film, it is possible to reduce the conductance between the current path and the surroundings and thus read out information easily from a small amount of accumulated charges. Moreover, SRAM, as described in IEICE Transactions, vol. E74, pp. 130-141, 1991, written by T. Masuhara et al, can be cited which is an example of the memory cell having a combination of FET (Field Effect Transistor) of polycrystalline silicon and MOS (Metal-Oxide-Semiconductor) transistor provided on the substrate surface. The SRAM in which a unit memory cell is formed as one set of six transistors uses polycrystalline silicon FET for two transistors that serve as load. Since the polycrystalline silicon FET can be formed on other transistors, the memory cell can be built in a smaller area than when six transistors are formed on the substrate surface.
Also, EPROM formed of polycrystalline silicon is known which is described in JP-A-05-082787 as an example of nonvolatile semiconductor memory having a channel on an insulator.
The semiconductor memory device that stores information by accumulating charges in storage regions within an insulator and using the change of conductance between the source and drain due to the increase or decrease of the accumulated charges, as represented by flash memory, has memory cells each formed of one transistor, and thus it is suited for its high-density integration. The flash memory has the merit of high-density integration and nonvolatile property, but it is three digits or more slower to rewrite than DRAM. Therefore, as in digital cameras, data is once stored in a volatile memory for buffer, and then gradually transferred to a nonvolatile element. Thus, since this technique needs to provide a buffer memory as a separate chip and use a complicated control system, the cost is greatly increased as compared with the case in which only a flash memory could be used. A register is provided for each data line on the flash memory chip. It can be considered to divide the data line and increase the number of registers, thereby raising the rewriting speed. However, since the register occupies a large area, the chip area would be increased, and thus the cost still rises.
In addition, if the capacitance of data line is reduced simply from the view point of improving the performance of semiconductor memory devices, the time necessary for charging and discharging is short at the time of writing, erasing or reading. Thus, such a device is suited for high-speed operation, and can operate with low consumption power because of a small amount of charges to be charged or discharged. This is true for word lines. On the other hand, the memory cell array region is still needed to expand in its area with the great increase of memory capacity even though the very small size capability is taken into consideration. Therefore, the data lines and word lines run between the ends of the array would become long, thus increasing their capacitance. A counter-measure for solving this problem can be used to divide the cell array into smaller units, and write or read for this unit. However, if peripheral circuits such as a sense amplifier and word line driving circuit are provided for each small unit, increase of the memory area will occur as a new problem.
Moreover, for cost reduction and improvement in speed of data transfer between memory and processor, the DRAM and flash memory should be designed to be on a single chip for the effective means. However, because the memory cell production process and the logic-purpose CMOS production process are not matched well with each other, it is difficult to combine both the memory performance and the logic performance.